The present invention relates generally to the design of application specific integrated circuits (ASIC). LSI Logic, the Assignee of the present invention, provides a design system called “FlexStream” (which is a registered trademark of LSI Logic (all rights reserved)). As shown in FIG. 1, the FlexStream® design system is configured such that an ASIC designer uses certain third party tools (i.e., implementation, verification and manufacturing test tools) to design an ASIC, and uses LSI Logic's Flex Stream® design system to analyze the design. The FlexStream® design system is a fully integrated environment for complex ASIC and System-on-Chip (SoC) design. It provides a complete system-to-silicon methodology that enables first-pass silicon success to meet tight time-to-market windows. The FlexStream® design system is an integration of best-in-class LSI Logic and third party EDA tools. This approach provides an ASIC designer with the flexibility to use their preferred tools. The ASIC designer designs with efficiency and confidence because LSI Logic's strong partnerships with EDA vendors assure that third party tools are well-integrated into the FlexStream® environment. In addition to design capabilities, the FlexStream® design system provides a link between all the design components—process technology, libraries, memories, CoreWare functions, advance packaging solutions, and manufacturing, test and assembly. While the FlexStream® design system which is currently available provides many advantages, it does not define a system or provide the necessary guidelines or information needed to effectively verify new test structures of an ASIC.
As design complexity increases, the testing requirements for those designs also increases. There are various kinds of tests which can be performed in an ASIC environment. There are also various kinds of test structures which can be introduced in a design. Each test structure has its own set of controls for testing. Each time a new test structure is introduced, a great amount of development and verification must occur before the test structure can be made available to the public. If the introduction of new test structures continues to grow at the current pace, the solutions for testing these test structures will become obsolete and virtually impossible to use.
Each test structure includes test pins (input and output) which need to be controlled or observed from the top level functional pins during manufacturing tests. Thus, the test pins and functional pins are shared. In order to accomplish sharing of the test pins and functional pins, certain structures, for example, boundary scan cells must be controlled. Another problem encountered is that with the growing number to test pins, a sufficient number of functional ports may not exist for sharing. Each test pin is associated with one or more control pin(s).
Currently, the test structures are designed through the use of software. However, using software to design the test structures requires a massive amount of development and is very error prone. Another problem encountered is that, if a designer creates his own test structures, it is almost impossible to verify the custom test structures along with standard test structures. In addition, it would be difficult to test whether the controls are operating properly, or if some of the controls need to be changed. Such testing of the controls would require communication between the development organization and users. Generally, the time needed for this communication is very lengthy and users do not receive the information they need in a timely fashion. Finally, to reduce the number of functional ports required for sharing, some test pins need to be combined for test purposes. With approximately 40 different types of test pins, implementing the combinations of test pins would be overwhelming.
Thus, adding new test structures to current designs is difficult. In addition, given the number of types of test pins, combining some test pins for functional test ports is extremely difficult. The current design methods also do not allow for the addition of custom test structures. Thus, introducing custom test structures to the ASIC design requires a significant amount of development time and verification time which may not be available. Finally, it the design does not operate as expected, and changes are needed, the changes can not be immediately implemented by the customer. Rather, the customer must request changes, the designer must implement the changes and then provide the customer with the changes which results in undesirable delays.